1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device that has a multi-layer insulating film as an interlayer insulating film for buried Cu wirings.
2. Background Art
In recent years, as the wiring pitch has been reduced in semiconductor integrated circuits, the problem of signal delay due to increase of the resistance of metal wirings and the capacitance of interlayer insulating films has become serious. In order to solve this problem, it has become essential to use Cu as the wiring material, and a low-dielectric-constant film (low-K film) as the interlayer insulating film. The interlayer insulating film for buried Cu wirings is formed of a multi-layer insulating film wherein a plurality of insulating films are laminated. In addition to the low-K film, the multi-layer insulating film has a Cu barrier film for preventing the diffusion of Cu from the underlying buried Cu wirings into the low-K film, an etching stopper film for forming wiring vias or trenches, a hard mask and the like.
The examples of the low-K films used herein include an MSQ (alkyl silsesquioxane polymer) film, an HSQ (hydrogenated silsesquioxane polymer) film, an SiOC film, and an organic polymer film, formed using a spin coating method or a CVD (chemical vapor deposition) method. An insulating film having pores of several angstroms to several hundred angstroms, known as a porous low-K film, is also promising for further reducing the dielectric constant of interlayer insulating films in next-generation semiconductor devices. In addition, various films such as an SiO2 film, SiN film, SiC film and SiCN film formed using a spin coating method or a CVD method are used as a Cu barrier film, an etching stopper film and the hard mask.
When various materials are combined to form a multi-layer insulating film, adhesion between different materials becomes poor due to difference in the properties of the materials, and a desired laminated structure cannot be obtained. Even if a desired laminated structure is obtained when initially formed, the multi-layer insulating film is peeled off at the boundary of the films due to mechanical stress from the CMP (chemical mechanical polishing) step in the subsequent formation of buried Cu wirings or the assembling step in the subsequent formation of buried Cu wirings, and reliability after completion is lost. If a porous low-K film is used, adhesion is further worsened, and the problem becomes more serious.
In order to solve these problems, in a conventional method for manufacturing a semiconductor device, plasma treatment is performed on the surface of a first insulating film in a single-gas atmosphere of N2, He, Ne, Ar, or the like, and then, a second insulating film is formed on the first insulating film, to improve the adhesion of the first and second insulating films (Japanese Patent Laid-Open No. 2000-106364).
However, the conventional method has a problem that the dielectric constant of the first insulating film increases due to the spattering effect or the densification effect, if a plasma treatment for improving adhesion is performed.